Clean Whole Cache on Cortex-A9

I am doing some benchmarking and I need to clear the cache before each test. I have this example here: Caches and Self-Modifying Code However, I just want to clean the whole cache. Is there an easy way...
pc hangs in process of cache setup - Cortex-A7

In ARM Cortex-A7 platform which includes L1 and L2 level caches，I start cache setup flow as follows: 1. Enable SMP bit and disable MMU. 2. Disable I cache in L1, and invalidate it , then enable...
How to configure L2 cache in Cortex-A7

Hi all, I am working on OrangePi board. The board configuration is, Quad-Core ARM Cortex-A7, 1.6 GHz 32 KB L1 I-Cache and 32 KB L1 D-Cache per core 512 KB L2-Cache I have few queries related...
L1 data cache and unified cache disabled in AMP mode for Cortex-a7

Hello Guys, in my system ( multi core cortex- a7 ), I do not want to be in SMP mode that means it is AMP mode and i need to clear the ACTLR.SMP bit to be in AMP mode but the strange thing which i found...
Cache Memory Requirement

Hi Experts, How to derive the cache memory requirement for the working of the software ? I could understand that each of the A/M/R processors have its own applications and build with its own Cache size...