• What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean?
    What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean? In ARM's white paper(about the cortex-A7 and cortex-A15) says as follow: I want ask the in-order and out-of-order...
  • The cortex-A7's pipeline support dual-issue, so I want to ask what's the dual-issue mean?
    The cortex-A7's pipeline support dual-issue, so I want to ask what's the dual-issue mean? I find some answers say that dual-issue means that the cortex-A7 can issue two instructions per clock. But in...
  • Where can I find the docments about how the ARM cortex-A series pipeline works?
    Where can I find the docments about how the ARM cortex-A series pipeline works? Such as the first step of the pipeline do what and the second step of the pipeline do what, and also the Cortex-A series...
  • What does it mean 'IT can be omitted'?
    Hi, When I read the following on ARM website, I don't understand the first line. When I change ITTE to TE (as ' IT can be omitted"), the assembler complains an error of this line. Could you explain it...
  • why inner attribute is affected by outer configuration?
    Hi expert: I am configuring a CortexA15 system. In the LPAE page table entry, SH[1:0] is configured as 11, so this is a Inner Shareable field. Then I need to set MAIR0.attr0 which is used by stage 1...