• Experimentation of Dual Issue
    Hi all, Can somebody specify asm code to experiment the dual issue of instructions and how the processor executes parallely ? Also i tried like performing LDM instruction followed by LSL instruction....
  • Cortex-A7 pipeline is non-symmetric, what does this attribute mean?
    Cortex-A7 pipeline is non-symmetric, what does this attribute mean? My understand is that cortex-A7 pipeline's five entries does not have the same two, in the contrary, the cortex-A15 have the two entries...
  • What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean?
    What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean? In ARM's white paper(about the cortex-A7 and cortex-A15) says as follow: I want ask the in-order and out-of-order...
  • Cortex-R4: Need a explanation for dual-issue restriction
    Hello, The following table is extracted from the Cortex-R4 whitepaper: Could someone help me to explain that question: My concern is that Cortex-R4 can take MOV as first instruction, ADD as second instruction...
  • Cortex-A8 : instruction fetch for dual-issue
    Hi, We experiment the following loop code (runs 4096 iterations) and we get CPI=0.66 (in other words, loop initiation interval (II) is about 6 machine cycles). We are trying really hard  to reason why...