Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2?

Hello, Consider following scenario: A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache. Now, the s/w writes...
Non-Cacheable memory and DMA on armv7a

Hi ! Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0). We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro...
When the data CPU wants to access is not in the cache the related block will always be copy to the cache, is this right?

When the data CPU wants to access is not in the cache the related block will always be copy to the cache, is this right? In the above question, the related region refers to the region seted to be cachealbe...
Which is better of thees CPUs

Which is better of thees CPUs: Cortex A53 octa core 1.5 ghz, Cortex A7 Allwinner T8 Eight core 2.0 ghz, Cortex A9 Quad-Core 1.8 ghz ?