• range of BL instruction in arm state
    range of BL instruction in arm state is + or - 32MB as per instruction set.how...........?
  • MRS/MSR (Banked register)
    What can be accessed by MRS/MSR in user mode? In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1): B9.3.10      MSR (Banked register) cond  0 0 0 1 0 R 0 0        M1      Rd  (0) (0) 1 M 0 0 0 0 (0...
  • UPREDICTABLE instructions
    Any idea about instructions marked as UNPREDICTABLE: can it then be UNDEFINED? In other words: UNDEFINED REQUIRES the instruction to cause UND-exception, but MAY UNPREDICTABLE do that, or does it...
  • What does this instruction do?
    In the ARMv7-A/R ARM Issue C I found two instructions with odd encoding: PUSH and POP, encoding A2. What's the Rt's role? I guess Rt and 'registers'-bitlist needs to match? Encoding A2 ARMv4*, ARMv5T...
  • Cortex-A9 PMU cycle counter not always incrementing at CPU frequency?
    Hello, I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU...