Funny asymmetry with banked register names

Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult. In document...
Still more stupid questions on Cortex-A7 instruction set

I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found an answer to in ARMv7-A/R ARM Issue C. How is this special? LDRD<c>_<Rt>,_<Rt2>,_<label>_LDRD...
What are hints?

What does it mean that an instruction is a hint instruction, like NOP, YIELD and WFE? I haven't found any explanations in ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, Issue C. ...
range of BL instruction in arm state

range of BL instruction in arm state is + or - 32MB as per instruction set.how...........?
I cannot write the sp register in the monitor mode

I use a Cortex-A7 board and write start up code. I try to use Security Extension. I use `smc` instruction and make cpu mode monitor mode. In the monitor handler, I tried to changed stack pointer value...