Information about ARM System control registers.

Hi all, I noticed there are multiple system control registers in ARM. The SCTLR_EL1 , SCTLR_EL2 and SCTLR_EL3. I want to know, what do multiple such system controls registers represent?? I am particularly...
Armv8 Memory Mapping

I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which...
Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

Hi, I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores. The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters...
why there are 4 cores per cluster in ARMV8 architecture

Hi experts, I want to knows why there are 4 core cores per cluster in ARM big.Littte architecture? Is it possiable if we make more cores per cluster? if not, what is the limitation?
Confusion about exception level of ARMv8

Hi, I am fairly new to ARM processor and start work with cortexA57 recently. After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8. 1. How...