translational table : block and table descriptor

Hello Experts, I am trying to understand in the attached snapshot, how the values of m and n are derived for table and block descriptors respectively ? Can anyone please explain me since I am...
Invalid entry - mmu page tables

Hi, I'm pretty much new to this. I have Level 2 table (for ARMv8 - 64KB granule) with multiple 512MB block entries inside. Some of those blocks are not valid (belong to the reserved/not accessible memory...
Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"?

I've gotten virtual memory working on ARMv8 after crafting the page tables. Oddly, _most_ of my translations are working (identity mapped) save for Flash which sits at physical address zero. I use a single...
Is it necessary to flush data cache of a modified page table entry?

Dear experts, Q0) why can't MMU observe the table entry change made by its company core ? working for Cortex-A55MP, EL1 in Aarch32, svc mode: Both 2 level of table entry are attributed as (inner...
making physical memory pages not cacheable (probabaly by modifying page table entry)

I need to make physical memory pages uncacheable, it seems that in armv7 (I am using arm cortex A9) there are some bits that determine the memory type. we have two level translations (so we have pgd and...