• coherence between R82 and other cpu or hardware modules
    Hi, There are two questions about coherence between R82 and others as: R82 only with a ACE5-LITE interface If R82 works with other 4 independent cpus with caches in a system to visit sharable...
  • Cache Coherence
    Hi ,    I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid.    1. Bring Core 1 out of reset.    2. Bring Core 2 out of reset.    3. Invalidate...
  • Parallelism between CPU and FPU
    Hi. I have a question regarding Cortex-M4 processor with floating point unit. Is it somehow possible to do some computation in parallel in CPU (with integers) and FPU (with floats)? Probably not, because...
  • AMBA 4 ACE and Hardware Cache Coherency - Top 5 Questions
    I thought I'd post a short blog post about commonly asked questions on AMBA 4 ACE and system coherency. What does ACE mean? ACE is the "AXI Coherency Extensions" introduced with the AMBA 4 specification...
  • Cache coherency in big.little system.
    Within an arm system, a cluster is an ACE master connected to the Arm CCI. To keep the cache coherency, the cluster would send some transactions to the bus and are trapped by the snoop filter of CCI....