• ARMv7 Branch Prediction Enable
    On "ARM Cortex -A Series Programmer’s Guide" , a piece of code is followed: ... @ Invalidate TLB MCR  p15, 0, r1, c8, c7, 0 @ Branch Prediction Enable MOV r1, #0 MRC p15, 0, r1, c1, c0, 0     @ Read Control...
  • indirect branches in ARMv8
    Please clarify that with me... With "The current Program Counter (PC) cannot be referred to by number as if part of the general register file and therefore cannot be used as the source or destination...
  • Disable Cache L1 et L2 Armv8
    Hi I work with the ARMV8 architecture, I want to disactivate L1 cache , to disable the L1 cache I found in the user manual "" The SCTLR.I bit enables or disables the L1 instruction cache. "" my...
  • Cortex-A9 Branch prediction to speculative execution
    Hi, I am building a cycle accurate simulator for the Cortex-A9 core, and so far I constructed most of the stages of the pipeline. However I am having trouble placing something that is not clear in any...
  • Cortex A9 (IMX6) : Enabling branch prediction aborts
    Hello, I am using imx6 (cortex- A9) board, and my mmu environment is as follows mmu - enabled L1 data cache - enabled L1 instruction cache - enabled D-side prefetch - enabled L2 cache - disabled Branch...