• [Cortex-A53] Exception Syndrome Register - Exception Class
    Hi, I'm searching for the documentation for the exception classes in ESR_ELx. But currently couldn't found any information. Want to port my bare-metal applications to AArch64. I own a PINE64 Rock64...
  • Exception Level Switch in ARMv8
    HI there: i am developing on a ARMv8 a57 based CPU, i want to disable the cache mechanism. it seems i need the access the corresponding registers in EL1 or above. i wonder how could i switch the EL...
  • Exceptions levels in the ARMv8 architecture
    Hello There are four exceptions levels in the ARMv8 architecture. EL0 EL1 EL2 EL3 Can anyone explain more of the EL3 execption level? What does it mean by 'allows swtiching between secure and nonsecure...
  • Confusion about exception level of ARMv8
    Hi, I am fairly new to ARM processor and start work with cortexA57 recently.  After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8. 1. How...
  • How to deice debug target exception level of watchpoint on ARMv8 architecture
    Hello, everyone I'm new to this community. I'd like to ask many questions and want to help someone. Now I have some difficulties in understanding aarch64's watchpoint exception handling scheme. I found...