• MRS/MSR (Banked register)
    What can be accessed by MRS/MSR in user mode? In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1): B9.3.10      MSR (Banked register) cond  0 0 0 1 0 R 0 0        M1      Rd  (0) (0) 1 M 0 0 0 0 (0...
  • AARCH64 banked registers
    I am failing at searches can someone point me to a reference for the banked registers for an FIQ in AARCH64 on a cortexA53 I can find hundreds of references for AARCH32 banked registers but none for...
  • Funny asymmetry with banked register names
    Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult. In document...
  • Cortex-A8 - accessing banked registers from monitor mode
    Note: This was originally posted on 20th March 2012 at http://forums.arm.com Hi Group, I am working on a Cortex A-8 Processor (ARMv7-a architecture). I am in the monitor mode and trying to access SP of...
  • Cortex-A9 core registers
    In RTL code of A9mp platform provided by ARM, I see that almost all registers are renamed and are out of order(There are registers named R0-R55). This make it quite difficult for me to debug some problems...