• AXI FIXED burst ; Wr/Rd narrow transactions.
    1. I'm examining AXI burst of FIXED type. 2. Data bus width is of 128bit. 3. case scenario WRITE :     awlen    = 2 (3 write transfers)     awsize  = 2 (32bit per each transfer)     awburst = 0 (FIXED...
  • Support for pipelining flops in AXI
    Hi All, Does ARM support pipelining flops in between valid/ready signals?Can someone explain why its *not* possible? Thanks
  • Difference between FIXED and INCR burst in AXI?
    For any burst transfer Master has to pass only first address, for the consecutive transfer address calculation is taken care by Slave. So i want to know what is the basic difference in FIXED and INCR...
  • Write interleaving with Multi-AXI master
    Hi, I have multiple questions related to multi-master AXI4 system. Eg: lets say we have 2 masters(m1,m2) and 2 slaves(s1,s2) and an interconnect. 1) In parallel, Can i have transfers(burst) to m1->s1...
  • MakeUnique Transaction (ACE protocol)
    Hi., As we know that there is a MakeUnique transaction in ace protocol, can anyone tell me how we can initiate this transaction..? I mean what is the respective signal in AXI4/ACE that allows us to set...