• [Cortex-A53] STP instruction stores out of the specified memory
    Hi Experts, I have a question about "STP" instruction in Cortex-A53. STP W6, W6, [SP, #20] --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted. I don't know why cause it....
  • Instruction Fault Generation
    Hi Experts, Is there any sample code or way to generate the Instruction Fault by forcing the processor (Cortex R). For Example, I tried below but no updates in IFSR (instruction fault status register...
  • Register 'names' in instruction descriptions
    The registers in the instructions are usually 'named' Rn, Rm, Rd, ... Is there some deeper meaning in the names? Usually Rd seems to mean 'destination register' Sometimes Rn is the only operand, sometimes...
  • Invalid state usage fault( INVSTATE ) for arm instruction
    Hi, We tried to execute a small assembly instruction function in .asm file for M7 core controller in GHS. But it initiated a hard fault exception with INVSTATE (Invalid state usage fault) bit is set...
  • Hard Faults and MemManage Faults in Cortex m3/m4
    I wrote a simple program, where I am writing to an illegal memory location. Writing in an illegal Memory location generates a MemManage fault. And if MemManage is not enabled, HardFault in generated....