• How AXI addressing works for fixed burst with unaligned address.
    Please consider following example: Data bus width = 32 bit burst size = 4 bytes Burst length = 3 Address = 0x02 burst type = FIXED. Write strobes are high from byte address 0x02 to the last byte in this...
  • axi problem
    Hi All I have two questions. Q1: is it ok that WVALID , WREADY and BVALID assert at the same cycle? Thanks! Q2: what is different between out of order and data interleaving ? Thanks!
  • AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...
  • axi ordering
    Hi the master is connected to axi-interconnect and two slaves(A and B) are connected to axi-interconnect. The master send a write transcation(AA) to slave A and then send a write transcation(BB) to slave...
  • AXI 4 burst boundary
    Hi All, I searched alot that why AXI 4 is having 4k boundary , but I didn't get the answer . Can any one explain deeply for this ???