• cortex M4 boot issue
    Hi Experts, I need your help... Actually i am work on a multicore controller, the master core loads the application for the slave core(cortex M4).. Now when the slave core starts, it executes c_int00...
  • SWD issue in Cortex-m0
    We are using Cortex-M0 DesignStart Pro to design MCU. When we use SWD to download grogram to flash in FPGA(Cortex_m0 mcu inside), we cannot to connect keil with FPGA, and Keil shows:" Could not stop Cortex...
  • Cortex M1 address translation issue
    Hi, I'm using a Pynq-Z1 board in which i'm trying to read the DDR memory of the PS with a Cortex M1 that is on the PL directly, without a CDMA or an intermediate BRAM . (This is the diagram i'm...
  • Cortex-m0 interrupt_demo simulation issue
    Hi, I am using Cortex-M0 DesignStart Pro. When I simulation intrrupt_demo test case, I found that IRQ[31:0] always 0, Is this correct? I saw the document , the interrupt_demo is Demonstration of interrupt...
  • Cortex M33 Multicore Boot issue
    Hello there! As I am exploring the Arm Musca A1 board in a multicore scenario, some doubts emerged. When I load each core program to the FLASH memory and then boot it up, each core loads it's own code...