• Cortex-M interrupts queue
    Hello, I want to ask how interrupts queue is implemented in ARM Cortex-M processors. For example while one ISR is processing if many other interrupts will arrive, how processor will handle this interrupts...
  • cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
  • How many interruptions the pendent queue supports?
    The queue for the processors interrupt context-m supports how many pending interruptions? Complementing please send me information where I can read more details about it. Thank you.
  • ARMCC V6.12 problem with simple std::queue
    Hi everyone! Im working with STM32F103VB, ARMCC V6.12, C++14(community) and have some problem with simple std::queue. When i write something like this: #include <queue> std::queue<int> Q; ...
  • Invalid Exception Class
    When debugging my bare metal app I'm getting an exception I don't understand. The processor is the Cortex-A53 The Exception occurs on "str q0, [sp, #96]" When reading ESR_EL1 i get 0x1FE00000 ...