• AHB transfer on Cortex-M3
    Hi, I am running following code in Cortex-M3. asm(" MOV R1,#0xFF0"); asm(" MOVT R1,#0xFFFF"); asm(" MOV R4,#0xAA0"); asm(" MOVT R4,#0xAAAA"); //start address asm(" MOV R3,#0x0000...
  • AMBA AHB TRANSFER CONTINUE AFTER ERROR RESPONSE
    Hello everyone, Please describe me the transfer continuation process after ERROR response from the slave. As shown in the above figure at cycle T4 if MASTER identifies the ERROR response from the SLAVE...
  • how can i design APB to AHB bridge ??
    i want to design a bridge between APB  and AHB in verilog my design consists of : 1. control clock unit (ccu)   // using APB 2. my DUT contains registers module & functional module  // using AHB 3. tow...
  • unaligned transfers
    Hi all i have some questions. Q1 if the master write a burst started in unaligned address. How to know the slave support unaligned transfers or not? Q2 AXI spec mention that the AXI protocol...
  • Early Burst Termination with IDLE transfer in Multi-Layer AHB Lite
    Hi, We are designing an Asynch slave operating over Multi Layer AHB Lite 3.0. I have come across some case which I am not sure how it should be handled. I am getting a predefined burst INCR16 ,...