• shareable domain and cache policy problem
    Hi, I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE...
  • shareable attribute in armv8
    Hi Experts,                     I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different. I could see how to set the different page attributes like...
  • shareability attribute for armv8 cortex a-53
    Hi, I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512. My question is how...
  • io coherency and shareability
    Hi, I have been reading about io coherency and the inner/outer shareability (SH bits in PTE). I kind of understand the concept of both but need help to connect the 2 concepts together. Lets assume a...
  • shareability memory attribute
    Hi ARM experts,     For shareability attribute, have some confusions:     1 For a memory location with cacheability attribute, does hardware do "flush" action after "writing" to push data to end if shareability...