• Is Cache Stashing introduced in DynamIQ similar to IO coherency?
    IO coherency also allows device to access coherent memory space. The only difference I noticed is that cache stashing connects device directly with cluster, however, IO coherency transactions need to...
  • ARMv8 memory ordering
    In the ARM Architecture Reference Manual issue D.a (ARM DDI 0487D.a) section K11.3.1 "Acquiring a lock" has the following example code: AArch32 Px PLDW[R1] ; preload into cache in unique state Loop...
  • Does Cortex-M0+ has a flash patch mechanism similar to the FPB function of Cortex-M4?
    Hello, As shown in title, does cortex-m0+ has flash patch and break point(FPB) function similar to cortex-m4, which will facilitate the upgrading of ROM code in the form of hardware. Thanks
  • indirect branches in ARMv8
    Please clarify that with me... With "The current Program Counter (PC) cannot be referred to by number as if part of the general register file and therefore cannot be used as the source or destination...
  • Armv8 Memory Mapping
    I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which...