How to flush write buffer when memory attribute is normal_nc

Hi, I am working on access pcie bar in armv8-a cpu(cortex-A5x) powered soc. Right now, I encounter an issue about (maybe) coherent issue. When I write data(4 bytes aligned) to pcie bar with ioremap_wc...
System Frequency for CortexA35

Hello, For a CortexA35, when reading the system counter clock frequency CNTFRQ_EL0 , I found out that the frequency is 8 MHz. Is this normal? For a target running in GHz? The target is i.MX8QXP...
Cache Coherence

Hi , I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid. 1. Bring Core 1 out of reset. 2. Bring Core 2 out of reset. 3. Invalidate...
ARM Cortex A9 flush cache

I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements. Is it doable from user mode? Processor: ARM Cortex...
Cortex-A35 cache partitioning

Hi, I am using a Cortex-A35 (Armv8-A) in a processor and I am looking for any technique that could allow the L2 unified cache to support partitioning between running processes (for non interference...