• Initial page table walk for secure/nonsecure accesses
    I have a basic concept question. From what I read in the ARMv8 docs... there is an NS and NSTable bit in the page table entries themselves for the 2nd level and higher page table lookups. So these can...
  • Teaching Scratchy to Walk with Neural Networks
    What would you do with a Cortex-M4 , a motor or two, some lego and a few cable ties? Well, if you’re Sebastian Förster, an embedded systems developer based in Germany, the answer is a small, four-legged...
  • A Walk Through the Cortex-A Mobile Roadmap
    Chinese Version中文版 Introduction The ARM Cortex-A mobile application processor product line spans several generations and three main product tiers. Developers and SoC designers experienced with one...
  • Is it necessary to flush data cache of a modified page table entry?
    Dear experts, Q0) why can't MMU observe the table entry change made by its company core ? working for Cortex-A55MP, EL1 in Aarch32, svc mode: Both 2 level of table entry are attributed as (inner...
  • Enable and disable MMU page table caching in L2
    Hello, I am using a dual core Cortex A9 CPU and I want to enable MMU caching in L2. By default all the DDR memory region is set as non-cacheable. But then I want only the DDR regions allocated...