A8: Keeping Cache-enabled and MMU-disabled

Hi all, A Question about the A8 processor. If I enable the L1 and L2 caches, I see a performance boost even if the MMU is disabled. I was under the impression that the MMU is required to be enabled...
Invalid entry - mmu page tables

Hi, I'm pretty much new to this. I have Level 2 table (for ARMv8 - 64KB granule) with multiple 512MB block entries inside. Some of those blocks are not valid (belong to the reserved/not accessible memory...
Can I enable and use D-Cache with disabled MMU?

Dear experts, I can't find any information whether d-cache could be used in ARMv8-A with disabled MMU. I found smth here - http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka8788.html...
Disabling the MMU

Hello everybody! I am working on a IMX-6 and i have a little problem with the MMU. I want to write on some registers which are blocked by the MMU, so i want to disable it. I went on this page ARM Information...
Enable MMU and d-cache on ARMv8 for u-boot

Hi, This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory...