Instruction width selection - forward/external reference

Hi, I am learning the Thumb 2 instruction set and at the moment I am trying to understand when to use the instruction width specifier. e.g.: ldmia.w sp!,{r3,lr} I understand sometimes it is necessary...
AXI4: Wider transactions than BUS width allowed?

Hi AXI-experts, Does AX4 support burst sizes larger than the bus width? Narrow transactions are allowed, but do wider transactions also work? Best regards, Robert
Are there any restrictions for the width of an address signal in an AXI4 interface?

Hello, in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an...
axi ordering

Hi the master is connected to axi-interconnect and two slaves(A and B) are connected to axi-interconnect. The master send a write transcation(AA) to slave A and then send a write transcation(BB) to slave...
AXI problem

Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...