Arm a53: Populate TLB without table walk?

Hi, From a previous question I got that setting the EPDx bits from the TCR_ELx register to 1 will disable table walk. Good starting point. But, should I access the same memory location again, it won...
Count Main TLB miss

Hello, experts: My platform is a Cortex-A9 MPCore CPU, Sabre Lite(i.mx6). I tried to count TLB miss so I implemented PMUEVENT to check micro TLB miss. But PMUEVENT doesn't support the main TLB miss...
Initial page table walk for secure/nonsecure accesses

I have a basic concept question. From what I read in the ARMv8 docs... there is an NS and NSTable bit in the page table entries themselves for the 2nd level and higher page table lookups. So these can...
Arm64 Long Format Translation Table Walk

Hi all - I'm trying to understand stage 1 translation. Assuming that the translation is starting at level 2, how do you determine the number of page table entries in the level 2 table? The documnetation...