ARM R5 and A53 cores coexist

I am fairly new to ARM development. Not quite sure where to post this - so I am starting here.. I have a virtualized chip (using QEMU) that has few R5 cores and few A53 cores. This physical chip is...
CPUID information about ARMv8 core

Hi experts, I want to know if there are CPUIDs information in CHI interface about IP A53/57 Mpcore? and can CCN504 transfer the CPUIDs to Slave device? for example, AXI_USER？ Thanks.
A53 core does not enter sleep state with WFE

I am trying to use WFE on Linux user space. I have the following code, while(1) { if (condition==TRUE) break; __asm__ __volatile__ ("wfe" : : : "memory"); ... } It seems the core never...
Barriers in in-order cores like cortex-A53, A7

Hi experts! As you know, power efficient arm like cortexA7, A53 has in-order pipleline. However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access. But...
To run library functions on arm a53 core

Hello experts, I am working on a53 core in which I am not able to run string library functions like memset, memcpy etc. I have included the string.h library also but it is generation an exception. The...