L2 cache error injection and Prefetch Abort

Hello, I am using an ARM dual core Cortex A9 as part of our satellite computer SoC, and I am now trying to inject errors in the different cache levels of the CPU. In particular I am trying to trigger...
Prefetch Abort in Cortex M processors

Hi, We are currently working with Cortex M4 processor and previously we worked with Cortex R5 processor. As part of our project requirement, we need to detect "prefetch abort" exception and to identify...
What is the difference between instruction prefetch and instruction pipelining in arm7tdmi?

In instruction pipe lining in arm7tdmi the next to next instruction from the instruction being executed is fetched in to the arm7 and we call it as fetching then what is difference between fetching of...
About PL310 cache controller and data aborts

Hello All, I am working on a automotive product based on i.MX6q and recently facing an issue where we see kernel error with message "imprecise external abort". I am trying to analyze it and need to know...
ARM Cortex A8 : Enabling D Cache aborts

I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU. I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another...