cache invalidation

Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
ARM1136: why the mismatch between cache stalls and cache misses ??

Something weird when I count both Instruction Cache Miss event and event 0x1 (viz. “Stall because instruction buffer cannot deliver an instruction. This could indicate an Instruction Cache miss or an...
Why is the I-cache designed as VIPT, while the D-cache as PIPT?

Hi, In Cortex-A8's architecture, I'm trying to understand why the I-cache is chosen to be in VIPT form (Virtually Indexed Physically Tagged), while the D-cache is PIPT (Physically Indexed Physically Tagged...
CAT Cache Allocation Technology) and CDP (code and Data Prioritization) features support

Hi, XEN 4.7 (last version of Hypervisor Xen) is supporting following cache features: - CAT Cache Allocation Technology - CDP Code and Data Prioritization Those features are supported by x86 L3 caches...
Cache type and cache operation sequence

I have a shared memory in DDR --- shared between two separate ARM execution environments (say A and B) in a heterogeneous compute SoC. SW on each execution units (A and B) Reads and Writes to this shared...