ACP and DMA usage on A53

Hi, I'm using DMA transfering data through ACP on A53. According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each...
Disabling L2 cache for CPU1 (Zynq-7000)

Hello people, we are trying to make AMP application on Zynq 7000 custom board. We have a FreeRTOS v8.2.3 and lwIP v1.4.1 running on CPU0, while baremetal application is running on CPU1 and this one...
Locked L2 cache (Pl310) Write issue through JTAG- Zynq 7000

We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG. From JTAG, Read works properly but writes makes the specific cache line corrupted, Step 1 : Initial...
Cortex M-3 on Zynq Evaluation and Development Board

I want to run Cortex M-3 soft processor core on ZedBooard. I have downloaded the cortex M-3 IP core, created a deisgn by integrating Zynq Processor with Cortex M-3 processor and generated bitstreams....
Why is there an ACP interface for many ARM processors?

Dear sirs, I read ACE specification and ARM processor documents for ACP explanation. I always have some questions about ACP. As soon as you know, ACP exists in SCU for data coherency. Q1: The document...