About AHB5 protection control signals

In AHB5, we have extended memory bits as [6:4] hprot. Previously we have [3:0] hprot. For implementation purpose, i treated [6:4] as a separate signal. This separate signal am qualifying based on some...
single-copy atomicity question for AHB5

Hi all~ I have some questions about AHB5 specification 1.If CPU(or another slave) is in 32-bit single-copy atomic group, can I only write/read a byte to it ? (HWDATA/HRDATA is 32bit-width, HBUST=SINGLE...
AMBA AHB5 : Stable Between Clock Question

Hi All, I have a question on AMBA5 AHB feature : Stable_between_Clock property The AMBA5 AHB Specification describes: Signals that are described as being stable are required to remain at the same...
AHB5 did'nt mention SPLIT and RETRY responses

While going through the AHB5 specifications, I did'nt find RETY and SPLIT responses anywhere. Did ARM remove these responses?
How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size?

Hello, I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I the system there will be a cortex A7 master(64bytes cache line). My question is:...