Cortex-A35 performance for DDR3 read accesses

Hi, I am using iMX 8X which has 1 cluster of 4 Cortex-A35 cores, with DDR3L (DDR3-1866) with ECC enabled. I performed some measurement for MEMCPY and MEMSET functions to have an estimate of the...
What ARMv8.x revision Cortex-A35 is?

Hi, ARMv8-A specification mentions revisions and options. I cannot find Cortex-A35 adheres to which exact version: ARMv8.1, 8.2, 8.3? I want to know which of the extensions described in the generic...
Cortex-A35 CoreMark results

Hi, I can't find CoreMark/MHz performance results for the Cortex-A35. Only DMIPS is available, but it is not always as reliable... Can you provide CoreMark results for A35? Thanks. Étienne
Cortex-A35 cache partitioning

Hi, I am using a Cortex-A35 (Armv8-A) in a processor and I am looking for any technique that could allow the L2 unified cache to support partitioning between running processes (for non interference...
A35 Power Mode Transitions

Has anyone come across documentation that tells how to calculate entrance and exit times from low-power modes where the L1 and L2 cache maintain data coherence? Thanks, Eric