ARMv7 how a program can check whether it is in secure state or not ?

I think all is in the title. When in secure, reading the SCR register with MRC will succeed. But in non secure state, the MRC fails and I don't get any undef or abort. Is it my mistake here ? Or it...
What does "low interrupt latency" means

Hi All, In R4 trm, there are some words about low interrupt latency. I have a question about it. " Low interrupt latency On receipt of an interrupt, the processor abandons any pending restartable memory...
Whether Armv7-A has a Write Buffer

Hi, Does Armv7-A have a write buffer? If yes, when will the write buffer be drained and what's the purpose of write buffer?
A Beginner’s Guide on Interrupt Latency - and Interrupt Latency of the Arm Cortex-M processors

Introduction All experienced embedded system designers know that interrupt latency is one of the key characteristics of a microcontrolller, and are aware that this is crucial for many applications...
MRS [A/C]PSR latency armv8-a?

HI, Do anyone has a clue on the latency of the MRS CPSR (or APSR) command? I want to read the flags with no jump (and it is critical). Thanks