Regarding ADFSR and AIFSR in ARM Cortex-A9 MPcore

Hello all, I was debugging an imprecise external abort in one of our product based on i.MX6q and came across a register - Auxiliary Data Fault Status Register readable and writable by the following instructions...
How to switch off 2nd core for Cortex-A9

I am using dual-core Cortex-A9 in a project where 1 core is enough. How to switch off another unused core?
ARM Cortex A9 second execution unit

Dear All, I am trying to understand the full working of execution stage in ARM cortex A9 and the types of instructions that are executed in second execution unit(ALU). Till now i was able to find quite...
Disabling L2 cache for CPU1 (Zynq-7000)

Hello people, we are trying to make AMP application on Zynq 7000 custom board. We have a FreeRTOS v8.2.3 and lwIP v1.4.1 running on CPU0, while baremetal application is running on CPU1 and this one...
cortex A9 multi-core

I'm learning cortex-a9 on freescale imx6 platform. How to start multi-core? And how to communicate between cores? I'm confused.