GIC-v3: optional asymetric / legacy support

Hi, how can I check if the GIC-v3 I am using has support for the optional asymetric / legacy support ? Best, V.
GIC-v3: control of group 0 interrupts activation and selection

Hi, I have two main questions, about the handling of group 0 interrupts: from my understanding of the GIC-v3 documentation, any secure OS (EL1, SCR.NS == 0) has access to ICC_IGRPEN0_EL1: Am I correct...
AArch64/GICv3:ICC_SGI1R_EL1: AFF1

I wonder, is AFF1 in ICC_SGI1R_EL1 also a bit-mask or does it address directly the cluster? So does AFF1 == 3 address cluster 3 or cluster 0 and cluster 1.
GICv3: setting G1SEN / G1NSEN in GICD_CTLR

During my experiment with GICv3 using ARM Foundation platform, I tried to set GICD_CTLR value from 0x0 to 0x37 (ARE S/NS + Enable G0, G1S and G1NS) and I got the surprise to see that the finale value...
GIC order of completion of interrupts

Hello, Reading the "ARM® Generic Interrupt Controller Architecture version 1.0 Architecture Specification" I read that "For nested interrupts, the order of interrupt completion must be the reverse of...