System wide cache flush

Hello, I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system: My need is to flush a cached memory area to RAM in order to be viewed by the M4 core...
shareability attribute for armv8 cortex a-53

Hi, I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512. My question is how...
Cache Coherence

Hi , I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid. 1. Bring Core 1 out of reset. 2. Bring Core 2 out of reset. 3. Invalidate...
Cache and store buffer maintenance in cortex-a8!

Dear All, Technical data sheets for the ARM7500FE and ARM7100 say that: "In the ARM Processor the cache will be searched regardless of the state of the C bit, only reads that miss the cache will be affected...
shareability memory attribute

Hi ARM experts, For shareability attribute, have some confusions: 1 For a memory location with cacheability attribute, does hardware do "flush" action after "writing" to push data to end if shareability...