making physical memory pages not cacheable (probabaly by modifying page table entry)

I need to make physical memory pages uncacheable, it seems that in armv7 (I am using arm cortex A9) there are some bits that determine the memory type. we have two level translations (so we have pgd and...
Invalid entry - mmu page tables

Hi, I'm pretty much new to this. I have Level 2 table (for ARMv8 - 64KB granule) with multiple 512MB block entries inside. Some of those blocks are not valid (belong to the reserved/not accessible memory...
is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

hi : I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*). however, I can not find any clue about flushing L2 cache to DRAM(if without L3). and I saw some points that...
ARM A64 Page table

Hi, I have a question on ARM page table. I am running a bare metal application on Cortex A72 and i have a failure with my application. Upon debugging the failure, i found an address which is contributing...
System wide cache flush

Hello, I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system: My need is to flush a cached memory area to RAM in order to be viewed by the M4 core...