Which ARMv8 register controls cache partitioning

Hi ARM folks, Which register controls the cache partitioning behavior on ARMv8 chips? My group is working with a Cavium ThunderX, and we're trying to experiment with different cache partitioning...
Cortex-A35 CoreMark results

Hi, I can't find CoreMark/MHz performance results for the Cortex-A35. Only DMIPS is available, but it is not always as reliable... Can you provide CoreMark results for A35? Thanks. Étienne
Memory partitioning on Cortex-A7

Hello, I am using a quad-core Cortex-A7 (on Raspberry PI 2). I run a Linux on Core 0,1,2 and a baremetal application on Core 3. My goal is to protect the baremetal application from the rest (i.e., the...
COrtex M7 cache hit rate measurement

Hello community, I have a Cortex M7 based product, and I want to measure the cache hit rate in different applications.compared to the cortex R5 the M7 does not embed a PMU. Do you have some idea on...
cache invalidation

Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...