• Clean and Invalidate Cache Memory
    Hi experts, Wat is the key difference between clean and invalidate the cache memory ? How it is related to eviction of data into the external memory ? What happens if any one of the operations alone carried...
  • Clean Whole Cache on Cortex-A9
    I am doing some benchmarking and I need to clear the cache before each test. I have this example here: Caches and Self-Modifying Code However, I just want to clean the whole cache. Is there an easy way...
  • clean and invalidate cache behavior before same address read
    I am running on cortex-A17. when following, step1: STR  R0, [R1]       ; [R1] is cacheable step2: DCCIMVAC          ; clean and invalidate cache step3: LDR  R0, [R1]       ; memory read Does step3 access...
  • Cache Coherence
    Hi ,    I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid.    1. Bring Core 1 out of reset.    2. Bring Core 2 out of reset.    3. Invalidate...
  • The merit of data cache cleaning
    Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message...