Cortex A code / function alignment

Hi ! I am writing assembly code for some ARMv7a and ARMv8a CPU. I know that code has to be 4 bytes aligned, but I saw in several places (uboot/linux) the ".align 4" GCC directive, which will align to...
Cortex-A9/GIC: de-activate an active interrupt

Hi my situation: Running an OS in normal-world which due to an (user) error enters safe state with interrupts disabled. The Hypervisor enters by an FIQ (watchdog) and should reset the normal-world. No...
ARM Cortex A9 flush cache

I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements. Is it doable from user mode? Processor: ARM Cortex...
Dhrystone Testing on Cortex A9: disabling Prints increases the DMIPS.

i am seeing an issue while doing Dhrystone test. i am using Dhrstone source code of version 2.1. when i run this source code on LINUX platform, i got DMIPS/MHz =1.6 but there are some printing commands...
Cortex-A9 PMU cycle counter not always incrementing at CPU frequency?

Hello, I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU...