Is it necessary to flush data cache of a modified page table entry?

Dear experts, Q0) why can't MMU observe the table entry change made by its company core ? working for Cortex-A55MP, EL1 in Aarch32, svc mode: Both 2 level of table entry are attributed as (inner...
ARMv8 mmu problem

Hi ARM experts, I have a problem in using armv8 mmu in bare-metal system: When using the 4KB translation granule, level 1 table which use D_Block convert VA to 1GB region PA. In Armv8 ARM page D4-1744...
Enable MMU and d-cache on ARMv8 for u-boot

Hi, This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory...
Why does ARM have 64KB Large Pages?

The ARM720T user manual mentions small and large pages. Since the ARM 720T requires a 64KB page table entry to be duplicated 16 times in the page table, why not place 16 small page (4KB) entries to mimic...
ARM A64 Page table

Hi, I have a question on ARM page table. I am running a bare metal application on Cortex A72 and i have a failure with my application. Upon debugging the failure, i found an address which is contributing...