ARMv7-A: Cache maintenance operation by VA, performance

Hi, according to this talk , cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop...
Cache and store buffer maintenance in cortex-a8!

Dear All, Technical data sheets for the ARM7500FE and ARM7100 say that: "In the ARM Processor the cache will be searched regardless of the state of the C bit, only reads that miss the cache will be affected...
Cortex-A8 Pipelined cache maintenance

Hi, I am new to the Cortex-A8, I would like to know what is the advantages of using "pipelined cache maintenance operations". "Auxiliary Control Register " has the "Cache maintenance pipeline" bit enabled...
Cache Coherence

Hi , I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid. 1. Bring Core 1 out of reset. 2. Bring Core 2 out of reset. 3. Invalidate...
MMU deactivation and I-Cache / Branch Predictor

Hi ! In order to call some functionality hard-coded in my board ROM (HAB from NXP i.MX6 board), I need to shut down the MMU: the ROM is not position independent. In particular, it is not always possible...