The Top 5 Things to Know about Cortex-A12

Introduction Smartphone and tablets are on the rise the increasing performance and convenience of these devices is definitely showing impact on the traditional PC market. Tablet sales will surge 53.4...
ARM Cortex-A17 / Cortex-A12 processor update

Since we launched Cortex-A17 and Cortex-A12 processors, we’ve seen wide adoption with customers planning to use these cores in a range of phones, tablets and other consumer devices. These ARMv7-A cores...
How to flush write buffer when memory attribute is normal_nc

Hi, I am working on access pcie bar in armv8-a cpu(cortex-A5x) powered soc. Right now, I encounter an issue about (maybe) coherent issue. When I write data(4 bytes aligned) to pcie bar with ioremap_wc...
Cache Coherence

Hi , I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid. 1. Bring Core 1 out of reset. 2. Bring Core 2 out of reset. 3. Invalidate...
What is difference between DCCIMVAC and DCIMVAC?

The DCIMVAC represents a cache invalidate work. But one specific remark is that it will clean the data if the data is dirty before invalidation. Refer to followings /*******************************...