purpose of RSDIS in ACTLR ?

Hello, What is the purpose of the RSDIS (Return Stack DISable) bit in ACTLR ? What would be the consequence on code execution if set DISable ? Is the software able to write this bit ? Thanks for help...
Cortex A9 single core

From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions: SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still...
pc hangs in process of cache setup - Cortex-A7

In ARM Cortex-A7 platform which includes L1 and L2 level caches，I start cache setup flow as follows: 1. Enable SMP bit and disable MMU. 2. Disable I cache in L1, and invalidate it , then enable...
How to configure L2 cache in Cortex-A7

Hi all, I am working on OrangePi board. The board configuration is, Quad-Core ARM Cortex-A7, 1.6 GHz 32 KB L1 I-Cache and 32 KB L1 D-Cache per core 512 KB L2-Cache I have few queries related...
Clean Whole Cache on Cortex-A9

I am doing some benchmarking and I need to clear the cache before each test. I have this example here: Caches and Self-Modifying Code However, I just want to clean the whole cache. Is there an easy way...