How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size?

Hello, I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I the system there will be a cortex A7 master(64bytes cache line). My question is:...
How to compute a cache size?

It might be a typo in the site, infocenter.arm.com/.../index.jsp . It should be 64KB (not 32KB) based on the picture. > Index (# of lines): 2^8 > # of Words per line: 2^4 > # of Bytes per word: 2^2...
How get ARMv7 cache size

Hi everybody!! I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15). In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the...
A72 Invalidate dirty cache line (DC IVAC)

The A53 TRM says that when you invalidate a dirty cache line (DC IVAC), then a clean is automatically performed before the invalidate. Does the A72 have the same behavior? Is it possible to invalidate...
ARM1176JZ-S, cache confg: effective cache size calculation

Note: This was originally posted on 22nd February 2009 at http://forums.arm.com Hello, 1) I am using ARM1176JZ-S core with WinCE Platform. The cache memory is configured as follows DCache: 128 sets...