Data synchronization Barrier and cache.

Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before...
PL310 cache synchronization

Hi ! I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation. - when I want to perform a synchronization, should I just wait for bit 0 (bit...
Synchronization Between CortexA and CortexM

Hello, I'm working with a bare-metal application running on i.MX8 (QuadCore CortexA35 & Single Core CortexM4). Currently, I use Load/Store executive assembly instructions along with memory attributes...
Which ARMv8 register controls cache partitioning

Hi ARM folks, Which register controls the cache partitioning behavior on ARMv8 chips? My group is working with a Cavium ThunderX, and we're trying to experiment with different cache partitioning...
ARMv8 PMU access

Hey guys, I'm running a sw in a multicore ARMv8 system and I'd like to know a bit more about the PMU component. There is a PMU per CPU, right? Is it possible from one CPU to access the other CPU...