Trouble configuring MMU for 2MB block mapping

So I'm working with QEMU and AArch64 mode and using the MMU. I've succesfully mapped 4K blocks, but I'm having trouble mapping 2M blocks. My configuration is such that the L1 entries are 1GB blocks, L2...
Disabling the MMU

Hello everybody! I am working on a IMX-6 and i have a little problem with the MMU. I want to write on some registers which are blocked by the MMU, so i want to disable it. I went on this page ARM Information...
How to design simple memory protection using MMU attributes & modes ?

Hello, Can anyone give some points as to how to design simple memory protection model, of standalone OS application composed tasks, each has its own region/section with attributes such as read only...
Secure world memory access with MMU disabled

Hi, I am a newbie to the TrustZone architecture. I learned that, in secure world, whether a memory access is secure or not is determined by the NS field in the translation descriptor and, in non-secure...
MMU and Cache configuration

Hello there, I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core. I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and...