Arm64 Long Format Translation Table Walk

Hi all - I'm trying to understand stage 1 translation. Assuming that the translation is starting at level 2, how do you determine the number of page table entries in the level 2 table? The documnetation...
Trouble configuring MMU for 2MB block mapping

So I'm working with QEMU and AArch64 mode and using the MMU. I've succesfully mapped 4K blocks, but I'm having trouble mapping 2M blocks. My configuration is such that the L1 entries are 1GB blocks, L2...
Different between AF vs AP (MMU Setup)

What is different between AF & AP? I understand AP = permission access as read/write/readonly/no access but what is AF?
MMU initialization for an ARM multicore system

I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib). On the shared SDRAM, I am planning to have dedicated...
Disabling the MMU

Hello everybody! I am working on a IMX-6 and i have a little problem with the MMU. I want to write on some registers which are blocked by the MMU, so i want to disable it. I went on this page ARM Information...