Trouble configuring MMU for 2MB block mapping

So I'm working with QEMU and AArch64 mode and using the MMU. I've succesfully mapped 4K blocks, but I'm having trouble mapping 2M blocks. My configuration is such that the L1 entries are 1GB blocks, L2...
MMU deactivation and I-Cache / Branch Predictor

Hi ! In order to call some functionality hard-coded in my board ROM (HAB from NXP i.MX6 board), I need to shut down the MMU: the ROM is not position independent. In particular, it is not always possible...
ARM Cortex A9 - Enabling/Disabling the Caches

Hello, I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9). In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches...
Different between AF vs AP (MMU Setup)

What is different between AF & AP? I understand AP = permission access as read/write/readonly/no access but what is AF?
Trustzone and caches

Hi, this question is following my work on the PL310 L2 cache of an imx6 board (see The specified item was not found. ). We are developing a secure OS that will run alongside Linux. At boot, our secure...