MMU - Permission Fault with EL1 access

Hello everyone, I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal). I've successfully...
MMU: force identity mapping without pages?

hi, on a cortex a53, I would like to get the best of both worlds. Having dcache enabled but no page walk in case of a miss. I want no memory protection because we manage the whole system ( kind of...
Arm64 Long Format Translation Table Walk

Hi all - I'm trying to understand stage 1 translation. Assuming that the translation is starting at level 2, how do you determine the number of page table entries in the level 2 table? The documnetation...
Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"?

I've gotten virtual memory working on ARMv8 after crafting the page tables. Oddly, _most_ of my translations are working (identity mapped) save for Flash which sits at physical address zero. I use a single...
Trouble configuring MMU for 2MB block mapping

So I'm working with QEMU and AArch64 mode and using the MMU. I've succesfully mapped 4K blocks, but I'm having trouble mapping 2M blocks. My configuration is such that the L1 entries are 1GB blocks, L2...