GIC500 + CPU Interface - CA53

Hi, I am triggering PPI or SGI interrupt on gic500 which will then communicate with CA53 over cpu interface and interrupt routine will be executed. After interrupt routine is executed, we can write...
Which processor has the most cores?

Which arm processor has the largest number or cores?
Cortex-A series's pipeline is for only one core or for all cores?

For example, in ARM's related docments says that cortex-A7 support max to 4 cores and cortex-A8 support only one core, and the same time cortex-A7's pipeline is not the same with cortex-A8's pipeline...
Understanding ARM NEON instruction

hi i am trying to understand ARM NEON instruction and encountered with vqrdmulh instruction. i am particularly interested in saturation case in instruction i am not getting any case with saturation ....
Why does Cortex-R only support most two cores?

Why does Cortex-R only support most two cores?